1. Field of the Invention
The present invention relates to a booster circuit used for reading data and such, and more particularly, to a booster circuit having function for controlling the boosting level within a desired range.
2. Description of the Related Art
Conventionally, a booster circuit is used for boosting of a word line when data stored in a semiconductor storage device is read. For example, a conventional booster circuit is described in Japanese Patent Application Laid-open No. 6-60651. FIG. 1 is a circuit diagram showing a conventional booster circuit described in Japanese Patent Application Laid-open No. 6-60651.
In the conventional booster circuit, a boost-starting signal ATDBST is input to an input terminal of an inverter 505, and a voltage Vboost is output from a boost node NDBST. An output terminal of the inverter 505 is connected to an input terminal of an inverter 506, a gate of an N-channel MOS transistor 503 and a gate of a P-channel MOS transistor 501. An output terminal of the inverter 506 is connected to one terminal of a boosting capacitor 507 whose capacity is Cb. The other terminal of the boosting capacitor 507 is connected to the boost node NDBST.
A drain of the N-channel MOS transistor 503 is grounded and a source thereof is connected to a drain of an N-channel MOS transistor 504. A source of the N-channel MOS transistor 504 is connected to a gate of a P-channel MOS transistor 502, and the junction point VX thereof is connected to one of input/output terminals of the P-channel MOS transistor 501.
Power source voltage VCC is always supplied to a gate of the N-channel MOS transistor 504, and the N-channel MOS transistor 504 is always in ON state. Further, one of input terminals of the P-channel MOS transistor 502 is connected to the power source voltage VCC, and the other input/output terminal is connected to the boost node NDBST. The other input/output terminal of the P-channel MOS transistor 501 is also connected to the boost node NDBST.
In the conventional booster circuit having the above-described structure, on standby before boosting, the boost-starting signal ATDBST is input to the inverter 505 at low level. The level of the boost-starting signal ATDBST is inverted by the inverter 505, and a signal of the level VCC is input to the input terminal of the inverter 506, the gate of the N-channel MOS transistor 503 and the gate of the P-channel MOS transistor 501.
With the above operation, the output signal of the inverter 506 is held at low level, and a low level signal is input to the boosting capacitor 507.
The N-channel MOS transistor 503 is brought into ON state, and the boost node NDBST and a gate level (node VX) of the P-channel MOS transistor 502 are held at low level. Therefore, the P-channel MOS transistor 502 assumes ON state. At that time, the P-channel MOS transistor 501 is kept in OFF state. As the P-channel MOS transistor 502 is turned ON, the power source voltage level VCC appears in the boost node NDBST as it is.
When the boost is started from that state, the boost-starting signal ATDBST is switched from low level to high level VCC and is input to the input terminal of the inverter 505.
With this operation, the output signal of the inverter 505 is inverted from high level VCC to low level, and the output signal of the inverter 506 is inverted from low level to high level VCC.
Therefore, a signal of high level VCC is applied to one terminal of the capacitor 507, a low level signal is input to the gate of the N-channel MOS transistor 503 and the gate of the P-channel MOS transistor 501. When the signal of high level VCC is applied to the one terminal of the capacitor 507, the boost node NDBST is boosted from the power source voltage level VCC to a voltage level shown in the equation (1) by capacitive coupling in the capacitor 507. EQU Vboost=(1+(Cb/Cb+C1))).times.VCC (1)
When the boost is completed, the input level of the boost-starting signal ATDBST is switched from high level to low level. Therefore, voltage level of each node is returned to level before boost is started. Then, the boost is completed.
When the above-described conventional booster circuit is used as booster means for a word line when data is read from a non-volatile semiconductor storage device, since it is necessary to secure both reading margin for on-cell and reading margin for off-cell, it is necessary to control the boost level within a range between the upper limit target and the lower limit target.
However, there is a problem that it is extremely difficult to give the highest priority to the achievement of the lower limit target, and to also achieve the upper limit target.
The reason is that there exist characteristics as dependence properties of power source voltage of boost level that the boost level is proportional to about two times of the power source voltage as shown in the equation (1).
Further, if the conventional booster circuit is used as boost means for a ward line when data is read from a non-volatile semiconductor storage device, when the voltage level of the word line is excessively increased, the gate level of memory cell is brought into boost level, the drain is brought into voltage level of about 1V, a pseudo weak writing mode is established. Therefore, reading is repeated and thus, there is a problem that variation is generated in a threshold value of the memory cell by the pseudo weak writing operation.
The reason is that there exist characteristics as dependence properties of power source voltage of boost level that the boost level is proportional to about two times of the power source voltage as described above.